Skill & TalentIndian Infrastructure27 Aug 2026

Semicon 2.0 to target 7nm-3nm chip technologies and train 100,000 design engineers.

The IT minister stated that Semicon 2.0 will target 7nm to 3nm chip technologies and support the training of 100,000 design engineers.

Why it matters

Design and process talent at this scale shapes how quickly advanced manufacturing capability can be absorbed in India.

Semicon 2.0
Talent
Design

Reported by Indian Infrastructure. MAECTRO summarises third-party developments for industry context and is not stated to be involved unless the original source says so.

Read the original announcement